Asic- Physical Design

Electromigration:  Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density.  This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses.  Failure Mechanisms There are two different EM failure mechanisms that occur due to asymmetry in the ion flow. The below shows a void where the outgoing ion flux exceeds the incoming ion flux, resulting in an open circuit. The second example shows a hillock where the incoming ion flux exceeds the outgoing ion flux, resulting in a short circuit. Fig: Open circuit and Short circuit Electromigration Dependen

Low Power Techniques: (1) Clock Gating: One-third to one-half of an IC design’s dynamic power is in the chip’s clock-distribution system.  Today, the two popular methods of clock gating are local and global . If you feed old data to the output of a flip-flop back into its input through a multiplexer, you typically need not clock again. Therefore, you can replace each feedback multiplexer with a clock-gating cell that clocks the signal off. You would then use the enable signal that controls the multiplexer to control the clock cell to clock the signal off. There are two types of clock gating: a) Latch free clock gating: b) Latch based clock gating (2) Multi-threshold technique:  TSMC  (Taiwan Semiconductor Manufacturing Co) offers a standard, or nominal, library; a high-speed library; and a low-power library, each having several types of cells. For instance, each of TSMC’s libraries includes low-threshold-voltage, high-threshold-voltage, and th

Temperature Inversion Effect: Let us first understand the basic concept of what causes the delay of the transistor from the below equation: Relation between current and delay of a mosfet   As you can find from the above that the more the current the less the delay of the PFET or NFET. Also you can refer to my previous blog on understanding the cell delay and transition. Now you understand that cell delay depends on the current. Let us see what current depends on Relation between mobility and current A phenomenon called lattice scattering happens at higher temperatures. Lattice vibrations cause the mobility to decrease with increasing temperature. Hence the resistance of a mosfet increases with increase in temperature causing current to reduce.  From the above figure we find that the current I is directly proportional to the mobility of the semiconductor. Hence as the mobility decreases, the current decreases. Hence cell delay increases. So , temperature increases ==&g

Special cells required for Multi-Voltage Design: (1) Level Shifter (2) Isolation Cell (3) Enable Level Shifter (4) Retention Flops (1) Level Shifter:  Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and Latch type level shifters are available. In general H2L LS’s are very simple, L2H LS’s are little complex and are in general larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths. With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale. (2) Isolation Cell:  These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an ‘always on’ region only and

Types of cells: Well taps (Tap Cells):  This is non-logic cells. Tap cells are needed to reduce substrate and well resistance to prevent latch up. These cells generally used when the all the standard or most of the cells does not have well or substrate. - It is inserted at specific interval in the design and distance is defined as per foundry rule for specific technology.  -We can insert at every row, every other row or stagger patterns also. - Most preferable way to insert the well tap is to stagger way because of reduce the total number of cells insertion in the design and reduce the total area utilization by those tap cells.  End cap Cells:   -This are the preplaced physical only cells. -Insert to meet certain design rules -Insert at the end of the site row, top and bottom side of the block boundary and every macro boundary.  - This will also helps to reduce the drc's nearer to macros as the standard cells do not placed near to the macros.  -This cells only

Setup and Hold Analysis Example: The following figure shows setup check with late (shown in solid line) launch clock and early capture clock (shown in dotted line). Figure 1 Setup Check The following figure shows hold check with early launch clock (shown in dotted line), and late capture clock (shown in solid line). Example 1 Setup Check in BC-WC Timing Analysis Mode In the following figure the software performs setup check on the path from FF1 to FF2. The software uses the Max library to scale all delays at WC conditions. The following values are assumed in this example: Clock source latency = none wire delay = 0 clock period = 4 Clock Mode = Propagated clock mode The software computes the slack as follows: Launch clock_late_path = 0.7 + 0.6 = 1.3 Data_late_path = 3.5 Capture clock_early_path = 0.7 + 0.5 = 1.2 Setup = 0.2 Data Arrival Time = 1.3 + 3.5 = 4.8 Data Required Time = 4 + 1.2 – 0.2 = 5 Slack = 5 - 4.8 = 0.2

Congestion: Congestion needs to be analyzed after placement results depends on how congested your design is. Congestion means number of required routing resources are more compared to available routing resources in the design. In simple words, number of required routing tracks is more compared to available routing tracks in the design. Routing congestion may be localized. Some of the things that you can do to make sure routing is hassle free are: Placement blockages:  The utilization constraint is not a hard rule, and if you want to specifically avoid placement in certain areas, use placement blockages. Soft blockages (buffer only) Hard blockages (No std cells and buffers are allowed to Place) Partial blockages (same as density screens) Halo (same as soft blockage but blockage can also be moved w.r.t Macro.) Macro-padding:  Macro padding or placement halos around the macros are placement blockages around the edge of the macros. This makes sure that no standard cell

Metal Filling: Whether performed by the designer or by the foundry, metal fill is a mandatory step at advanced nodes to ensure manufacturability and high yield. It involves filling the empty or white spaces near the design with metal polygons to ensure regular planarization of the wafer. Foundry-mandated fill requirements stipulate that the fill density be within specified maximum and minimum parameters. While regular planarization is crucial to prevent over or under polishing of signal routes and active circuitry, metal fill can also negatively affect timing due to increased capacitive coupling to the nearby nets. Thus, the designer must ensure that the metal fill is done without impacting timing-critical nets. In other words, the fill needs to be timing-aware. Timing-awareness is also needed when the engineering change order (ECO) arrives late in the design cycle. The ECOs require the designer to change the layout and fill around the affected area. Thus, the fill method

Floorplan: Floor planing is the starting step in ASIC physical design. For example, before building the house, planning for the exact location of each end every room is similar to the ASIC’s floor planning process. Building’s blue-print planning will be a better example for ASIC floor planning.  Detailed process of floor planning is explained below with necessary diagrams. Floor plan determines the size of the design cell (or die), creates the boundary and core area, and creates wire tracks for placement of standard cells. It is also a process of positioning blocks or macros on the die. First step is to define the total size of the die. Two types of design are possible. Block level designs will be rectilinear and chip level designs will be rectangular in shape. Rectilinear – To define this size more coordinates are required Rectangular – To define this only height and width of the die is required The following parameters are decided in the floor planning stage. Die size,

Static Timing Analysis: Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations without having to simulate . No vector generation is required ,no functionality check is done Why is timing analysis important when designing a chip? Timing is important because just designing the chip is not enough; we need to know how fast the chip is going to run, how fast the chip is going to interact with the other chips, how fast the input reaches the output etc…Timing Analysis is a method of verifying the timing performance of a design bychecking for all possible timing violations in all possible paths. Why do we normally do Static Timing Analysis and not Dynamic Timing Analysis? What is the difference between them? Timing Analysis can be done in both ways; static as well as dynamic. Dynamic Timing analysis requires a comprehensive set of input vectors to check the timing characteristics of the paths