Skip to main content

EM

Electromigration: 

Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density. 
This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses. 

Failure Mechanisms

There are two different EM failure mechanisms that occur due to asymmetry in the ion flow. The below shows a void where the outgoing ion flux exceeds the incoming ion flux, resulting in an open circuit. The second example shows a hillock where the incoming ion flux exceeds the outgoing ion flux, resulting in a short circuit.

Fig: Open circuit and Short circuit


Electromigration Dependency on Physical Effects:

1) Temperature:

Electromigration is dependent on temperature, however, there is a more sinister dependence on temperature that accelerates failures due to voids. Below figure highlights a cyclical positive feedback loop that ultimately ends in failure.


Once a void begins to develop in a metal wire, the wire itself becomes narrower at that point. Due to the reduction in width, the current density increases and, therefore, the interconnect temperature increases due to Joule heating. Joule heating is a result of root-mean square (RMS) current. As the temperature of the wire increases, the growth of the void accelerates, and eventually an open circuit occurs.

2) Wire Width:

Current density is the primary factor influencing electromigration. By increasing the wire width, current density is reduced and susceptibility to EM is reduced.  

3) Wire Length:

There is a lower limit for the length of interconnect that will be subjected to the effects of electromigration. It is known as “Blech length”, and any wire that has a length below this limit will not fail by electromigration.

Comments

Post a Comment

Popular posts from this blog

Special cells and their Importance

Types of cells: Well taps (Tap Cells):  This is non-logic cells. Tap cells are needed to reduce substrate and well resistance to prevent latch up. These cells generally used when the all the standard or most of the cells does not have well or substrate. - It is inserted at specific interval in the design and distance is defined as per foundry rule for specific technology.  -We can insert at every row, every other row or stagger patterns also. - Most preferable way to insert the well tap is to stagger way because of reduce the total number of cells insertion in the design and reduce the total area utilization by those tap cells.  End cap Cells:   -This are the preplaced physical only cells. -Insert to meet certain design rules -Insert at the end of the site row, top and bottom side of the block boundary and every macro boundary.  - This will also helps to reduce the drc's nearer to macros as the standard cells do not placed near to the macros...
Post a Comment
Read more

PD Interview Questions with Answers

PD Interview Questions with Answers: 1) How can you reduce dynamic power? – Reduce switching activity by designing good RTL - Clock gating -Architectural improvements -Reduce supply voltage -Use multiple voltage domains-Multi vdd 2) What are the vectors of dynamic power? Voltage and Current 3) How will you do power planning? 4) If you have both IR drop and congestion how will you fix it? -Spread macros -Spread standard cells -Increase strap width -Increase number of straps -Use proper blockage 5) Is increasing power line width and providing more number of straps are the only solution to IR drop? -Spread macros -Spread standard cells -Use proper blockage 6) In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why? (buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you m...
Post a Comment
Read more

Standard cells placement

Placement stage during PnR: As a basic function of placement stage is the placement of standard cells and their legalization based on certain factors. once floorplan/powerplan stage is ready then block owners need to check certain sanity checks like macro placement is proper or not, it is violating the macro spacing guidelines or not, special cells placed proper or not, port placement proper or not, power plan with all the layers incorporate in the design or not and so on. There are many other checks required to check before move to the placement stage.  Placement stage followed by the floorplan stage.We have to set many variables related to timing/congestion analysis effort at internal stage of placement step and so on, which are depends on block complexity and user requirement. For example, if the design is critical in terms of timing, then users can set the timing optimization efforts to high from medium, so at the time of placement optimization, tool can more focus to timing an...
Post a Comment
Read more