Skip to main content

Metal Filling Styles

Metal Filling:
Whether performed by the designer or by the foundry, metal fill is a mandatory step at advanced nodes to ensure manufacturability and high yield. It involves filling the empty or white spaces near the design with metal polygons to ensure regular planarization of the wafer. Foundry-mandated fill requirements stipulate that the fill density be within specified maximum and minimum parameters.

While regular planarization is crucial to prevent over or under polishing of signal routes and active circuitry, metal fill can also negatively affect timing due to increased capacitive coupling to the nearby nets. Thus, the designer must ensure that the metal fill is done without impacting timing-critical nets. In other words, the fill needs to be timing-aware. Timing-awareness is also needed when the engineering change order (ECO) arrives late in the design cycle. The ECOs require the designer to change the layout and fill around the affected area. Thus, the fill methodology should allow easy removal and re-insertion of fill without violating timing of the nearby nets.

To optimally fill the design while minimizing the capacitive coupling, foundries have responded with increasingly sophisticated requirements to achieve the requisite fill density. As an example, while the place-and-route guided track-based fill on the left of Figure 1 can potentially cause higher capacitive coupling with the adjacent signal nets, the physical verification guided staggered and signoff fill pattern on the right delivers better white space coverage while reducing capacitive coupling. Since the staggered fill is coded as signoff requirements in a physical verification runset, the resulting fill from such runsets can be called signoff metal fill.
For advanced nodes, it is also necessary for metal-fill methodology to support large hierarchical designs to enable higher productivity. Such designs can be efficiently verified with an easy way to skip re-filling a pre-filled block since, in a typical design flow, the designer utilizes pre-filled blocks supplied by IP and core providers. These providers have already carefully closed timing after metal fill insertion.

Comments

Post a Comment

Popular posts from this blog

Special cells and their Importance

Types of cells: Well taps (Tap Cells):  This is non-logic cells. Tap cells are needed to reduce substrate and well resistance to prevent latch up. These cells generally used when the all the standard or most of the cells does not have well or substrate. - It is inserted at specific interval in the design and distance is defined as per foundry rule for specific technology.  -We can insert at every row, every other row or stagger patterns also. - Most preferable way to insert the well tap is to stagger way because of reduce the total number of cells insertion in the design and reduce the total area utilization by those tap cells.  End cap Cells:   -This are the preplaced physical only cells. -Insert to meet certain design rules -Insert at the end of the site row, top and bottom side of the block boundary and every macro boundary.  - This will also helps to reduce the drc's nearer to macros as the standard cells do not placed near to the macros...
Post a Comment
Read more

Antenna Effect

Antenna Effect: Process antenna effect or “plasma induced gate oxide damage” is a manufacturing effect. i.e. this is a type of failure that can occur solely at the manufacturing stage. The gate damage that can occur due to charge accumulation on metals and discharge to a gate through gate oxide. Let us see how this happens. In the manufacturing process, metals are built layer by layer. i.e. metal1 is deposited first, then all unwanted portions are etched away, with plasma etching. The metal geometries when they are exposed to plasma can collect charge from it. Once metal1 is completed, via1 is built, then metal2 and so on. So with each passing stage, the metal geometries can build up static electricity. The larger the metal area that is exposed to the plasma, the more charge they can collect. If the charge collected is large enough to cause current to flow to the gate, this can cause damage to the gate oxide. This happens because since the layers are built one-by-one, a source/d...
Post a Comment
Read more

Temperature Inversion effect at lower technology nodes- How it will impact on cell delay

Temperature Inversion Effect: Let us first understand the basic concept of what causes the delay of the transistor from the below equation: Relation between current and delay of a mosfet   As you can find from the above that the more the current the less the delay of the PFET or NFET. Also you can refer to my previous blog on understanding the cell delay and transition. Now you understand that cell delay depends on the current. Let us see what current depends on Relation between mobility and current A phenomenon called lattice scattering happens at higher temperatures. Lattice vibrations cause the mobility to decrease with increasing temperature. Hence the resistance of a mosfet increases with increase in temperature causing current to reduce.  From the above figure we find that the current I is directly proportional to the mobility of the semiconductor. Hence as the mobility decreases, the current decreases. Hence cell delay increases. So , temperature ...
Post a Comment
Read more