Skip to main content

Different cells for multi Power domain designs

Special cells required for Multi-Voltage Design:


(1) Level Shifter
(2) Isolation Cell
(3) Enable Level Shifter
(4) Retention Flops
(1) Level Shifter: Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and Latch type level shifters are available. In general H2L LS’s are very simple, L2H LS’s are little complex and are in general larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths. With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale.
(2) Isolation Cell: These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an ‘always on’ region only and the enable signal of the isolation cell needs to be ‘always_on’. In a nut-shell, an  isolation cell is necessary to isolate floating inputs.

(3) Enable Level Shifter: This cell is a combination of a Level Shifter and a Isolation cell.
(4) Retention Flops: These cells are special flops with multiple power supply. They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down. All the paths leading to this register need to be ‘always_on’ and hence special care must be taken to synthesize/place/route them. In a nut-shell, “When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used”.
The retention flop has the same structure as a standard master-slave flop. However, the retention flop has a balloon latch that is connected to true-Vdd. With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch. Similarly, when the block comes out of sleep, the data can be written back into the flip-flop.

Comments

Post a Comment

Popular posts from this blog

Special cells and their Importance

Types of cells: Well taps (Tap Cells):  This is non-logic cells. Tap cells are needed to reduce substrate and well resistance to prevent latch up. These cells generally used when the all the standard or most of the cells does not have well or substrate. - It is inserted at specific interval in the design and distance is defined as per foundry rule for specific technology.  -We can insert at every row, every other row or stagger patterns also. - Most preferable way to insert the well tap is to stagger way because of reduce the total number of cells insertion in the design and reduce the total area utilization by those tap cells.  End cap Cells:   -This are the preplaced physical only cells. -Insert to meet certain design rules -Insert at the end of the site row, top and bottom side of the block boundary and every macro boundary.  - This will also helps to reduce the drc's nearer to macros as the standard cells do not placed near to the macros...
Post a Comment
Read more

Antenna Effect

Antenna Effect: Process antenna effect or “plasma induced gate oxide damage” is a manufacturing effect. i.e. this is a type of failure that can occur solely at the manufacturing stage. The gate damage that can occur due to charge accumulation on metals and discharge to a gate through gate oxide. Let us see how this happens. In the manufacturing process, metals are built layer by layer. i.e. metal1 is deposited first, then all unwanted portions are etched away, with plasma etching. The metal geometries when they are exposed to plasma can collect charge from it. Once metal1 is completed, via1 is built, then metal2 and so on. So with each passing stage, the metal geometries can build up static electricity. The larger the metal area that is exposed to the plasma, the more charge they can collect. If the charge collected is large enough to cause current to flow to the gate, this can cause damage to the gate oxide. This happens because since the layers are built one-by-one, a source/d...
Post a Comment
Read more

Low Power Basic Understanding

Low Power Techniques: (1) Clock Gating: One-third to one-half of an IC design’s dynamic power is in the chip’s clock-distribution system.  Today, the two popular methods of clock gating are local and global . If you feed old data to the output of a flip-flop back into its input through a multiplexer, you typically need not clock again. Therefore, you can replace each feedback multiplexer with a clock-gating cell that clocks the signal off. You would then use the enable signal that controls the multiplexer to control the clock cell to clock the signal off. There are two types of clock gating: a) Latch free clock gating: b) Latch based clock gating (2) Multi-threshold technique:  TSMC  (Taiwan Semiconductor Manufacturing Co) offers a standard, or nominal, library; a high-speed library; and a low-power library, each having several types of cells. For instance, each of TSMC’s libraries includes low-threshold-voltage, high-threshold-v...
Post a Comment
Read more