Low Power Basic Understanding

Low Power Techniques:

(1) Clock Gating:

One-third to one-half of an IC design’s dynamic power is in the chip’s clock-distribution system. Today, the two popular methods of clock gating are local and global. If you feed old data to the output of a flip-flop back into its input through a multiplexer, you typically need not clock again. Therefore, you can replace each feedback multiplexer with a clock-gating cell that clocks the signal off. You would then use the enable signal that controls the multiplexer to control the clock cell to clock the signal off.

There are two types of clock gating:

a) Latch free clock gating:

b) Latch based clock gating

(2) Multi-threshold technique: 

TSMC (Taiwan Semiconductor Manufacturing Co) offers a standard, or nominal, library; a high-speed library; and a low-power library, each having several types of cells. For instance, each of TSMC’s libraries includes low-threshold-voltage, high-threshold-voltage, and threshold-voltage-with-MTCMOS (multithreshold-CMOS) cells. Multiple-cell libraries help designers deal with both leakage and dynamic power. To deal with leakage power using multiple types of cells, designers today employ multithreshold design. “Because we’ve played so many games with V_DD and V_TH[threshold voltage], we can’t create one library that is going to work for an entire design, because you have designs that are speed-critical, and, for the areas that are not speed-critical, you want to reduce the leakage.”  

A multicell library typically comprises at least two sets of identical cells that have different threshold voltages. Those with higher threshold voltage are slower but have less leakage; conversely, the cells with lower threshold voltage are faster but leak. “

For most applications, designers typically use a low-threshold-voltage library for a first pass through synthesis to get maximum performance and meet timing goals. They then determine the critical paths in their design—that is, the path or paths in the design that require the highest performance. They then try to locate areas that don’t require low-threshold-voltage cells and swap out low-voltage cells for high-voltage cells to reduce overall power and leakage of the design.

(3) Multi voltage Technique:

Although multithreshold design helps engineers minimize leakage of their designs through the use of multiple libraries, another technique, multivoltage design, helps designers control dynamic power. Similar to multithreshold design, multivoltage design enables designers to give the critical paths and blocks in their designs access to maximum voltage for the process and specification, but the designers then reduce the voltage for less power-hungry blocks.

For example, a processor block may require a clock speed of 500 MHz, but a USB core may require only 30 MHz to comply with the USB protocol and thus require less voltage to run. So, if designers give the USB core only the power it needs, they can drastically reduce the overall power the design consumes. To implement the method, designers traditionally put level shifters between blocks that are running at different voltages. “If you have a 0.9V region on your IC design that is sending a signal to a 1.2V region, you have to put a level shifter between the two regions so you can boost it to the swing in voltage and control timing.”

(4) Power Gating:

Like voltage gating, power gating involves temporarily shutting down blocks in a design when the blocks are not in use. And, like voltage gating, the technique is complex. “The neat thing about the other techniques is that they are pretty much all transparent to the design engineer.”  I have to design a power controller that is going to control what blocks I need to shut down and when, and I have to think about what voltage I’m going to [need to] run different blocks.”

Traditionally, two methods for power gating are fine-grained and coarse-grained. In fine-grained power gating, designers place a switch transistor between ground and each gate. This approach allows designers to shut off the connection to ground whenever a series of functions is not in use. “You do that [technique] with every cell in the library."“At first, people really liked fine-grained power gating because it is fairly easy to do power characterization of each cell, but the problem is the area hit is very significant: two to four times larger.” Designers can also mix and match cells, having some power-gated and others not. Cells with high threshold voltage need not use power gating. For the most part, the power penalty is just too large, and many design groups are instead using coarse-grained power gating, in which designers create a power-switch network—essentially, a group of switch transistors that in parallel turn entire blocks on and off. The technique does not have the area hit of the fine-grained technique but is harder to characterize on a cell-by-cell basis.

The method requires either manual or tool-automated insertion of isolation-retention flip-flops. “When you shut down a block, and its outputs go to a block that is still powered up, you have to worry about those power-down nodes floating, and they can float to the threshold voltage and create unwanted currents downstream.” 

I have publish Paper on Low Power Techniques on IJSRD. Please refer below link to understand all the low power techniques. 

Please refere below article publish by me to get the more idea about low power techniques. 

http://ijsrd.com/Article.php?manuscript=IJSRDV2I4285