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Special cells and their Importance

Types of cells:

Well taps (Tap Cells): This is non-logic cells. Tap cells are needed to reduce substrate and well resistance to prevent latch up. These cells generally used when the all the standard or most of the cells does not have well or substrate.
- It is inserted at specific interval in the design and distance is defined as per foundry rule for specific technology. 
-We can insert at every row, every other row or stagger patterns also.
-Most preferable way to insert the well tap is to stagger way because of reduce the total number of cells insertion in the design and reduce the total area utilization by those tap cells. 




End cap Cells: 
-This are the preplaced physical only cells.
-Insert to meet certain design rules
-Insert at the end of the site row, top and bottom side of the block boundary and every macro boundary. 
- This will also helps to reduce the drc's nearer to macros as the standard cells do not placed near to the macros. 
-This cells only have VDD-GND pins and no other logical pins. 



Decap Cells: They are temporary capacitors which are added in the design between power and ground rails to counter the functional failure due to dynamic IR drop. Dynamic IR Drop happens at the active edge of the clock at which a high current is drawn from the power grid for a small duration. If power source is far from a flop the chances are there that flop can go into metastable state. To overcome decaps are added, when current requirement is high this decaps discharge and provide boost to the power grid.

decap cell.

Tie Cells: Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In Lower technology nodes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. These cells are part of standard-cell library. The cells which require Vdd (Typically constant signals tied to 1) connect to Tie high cells The cells which require Vss/Gnd (Typically constant signals tied to 0) connect to Tie Low cells.



 Filler cells: Filler cells are used to establish the continuity of the N- well and the implant layers on the standard cell rows, some of the small cells also don’t have the bulk connection (substrate connection) because of their small size (thin cells). In those cases, the abutment of cells through inserting filler cells can connect those substrates of small cells to the power/ground nets. i.e. those thin cells can use the bulk connection of the other cells (this is one of the reason why you get standalone LVS check failed on some cells).



Spare cells: These are just that. They are extra cells placed in your layout in anticipation of a future ECO. When I say future, I mean after you taped out and got your silicon back. After silicon tests complete, it might become necessary to have some changes to the design. There might be a bug, or a very easy feature that will make the chip more valuable. This is where you try to use the existing “spare” cells in your design to incorporate the design change. For example, if you need a logic change that requires addition of an AND cell, you can use an existing spare AND to make this change. This way, you are ensuring that the base layer masks need no regeneration. The metal connections have changed, and hence only metal masks are regenerated for the next fabrication.

Kinds of spare cells: There are many variants of spare cells in the design. Designs are full of spare inverters, buffers, nand, nor and specially designed configurable spare cells.


 

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