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Timing Analysis

Setup and Hold Analysis Example:

The following figure shows setup check with late (shown in solid line) launch clock and early
capture clock (shown in dotted line).

 Figure 1 Setup Check


The following figure shows hold check with early launch clock (shown in dotted line), and late
capture clock (shown in solid line).


Example 1 Setup Check in BC-WC Timing Analysis Mode



In the following figure the software performs setup check on the path from FF1 to FF2.
The software uses the Max library to scale all delays at WC conditions.

The following values are assumed in this example:
Clock source latency = none
wire delay = 0
clock period = 4
Clock Mode = Propagated clock mode
The software computes the slack as follows:
Launch clock_late_path = 0.7 + 0.6 = 1.3
Data_late_path = 3.5
Capture clock_early_path = 0.7 + 0.5 = 1.2
Setup = 0.2
Data Arrival Time = 1.3 + 3.5 = 4.8
Data Required Time = 4 + 1.2 – 0.2 = 5
Slack = 5 - 4.8 = 0.2

Example 2 Hold Check in BC-WC Timing Analysis Mode

In the following figure the software performs hold check on the path from FF1 to FF2.


The software uses the Min library to scale all delays at BC conditions.
The following values are assumed in this example:

Clock source latency = none
wire delay = 0
clock period = 4
Clock Mode = Propagated clock mode
The software computes the slack as follows:
Launch clock_earlypath = 0.5 + 0.4 = 0.9
data_earlypath = 1.0
Capture clock_latepath = 0.3 + 0.5 = 0.8
hold = 0.1
Data arrival time = 0.9 + 1 = 1.9
Data Required Time = 0.1 + 0.8 = 0.9
Slack = 1.9 - 0.9 = 1


Now in any situation setup timing is violated then what are the different techniques will be use to fix the timing violations at the time of ECO stage(after PnR).

Setup violations Fixing Techniques:
1) We can convert lower drive strength cells to higher drive strength cells (VT change- from SVT/LVT to ULVT)
2) Upsize the cells (We can increased the drive size. for example, a2-> a4, a6-> a8 or so)
3) Reduce the data path delay 
4) If any cells have high cell delay because of net routed in lower metal layer or detouring occur, then we improve the net routing which will help to fix setup violations
5) We can use late clocking concepts. It means adding delay in clock capture path to fix the setup violations. But we can choose late clocking as a last option because it will create other violations as the same clock is going to too many flops. 

Hold Violations Fixing Techniques:
1) change the cells to lower VT cells
2) downsize the cells
3) Add delay in data path 
4) Do the routing to lower metal layer
5) Do the Early clocking

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