Skip to main content

Basic PD Interview Questions

PD interview questions

ASIC physical design basic interview question answers:
  1.  ASIC design flow.
  2.  Inputs/outputs of the ASIC design flow.
  3.  What is synthesis?
  4.  What is clock jitter ?
  5.  What are the timing optimization techniques used in Synthesis?
  6.  Macro placement guidelines.
  7.  How to decide floorplan size and shape, pin placement?
  8.  What are the important checks after placement?
  9.  What is congestion ? how to reduce the congestion?
  10.  What is the difference between HFN and CTS?
  11.  What is skew and latency?
  12.  How to achieve skew and latency targets?
  13. Which is more preffered in CTS? buffers or inverters?
  14.  How to optimize the max_tran, max_cap violations.
  15. Clock balancing with generated clocks.
  16. Handle asynchronous clocks during CTS.
  17. SI issues, Crosstalk delay, crosstalk noise,
  18. What is NDR (Non-Default rule) ? How DRC will be affected due to NDR? Can you relax NDR to resolve DRC's?
  19.  Which are the DFM issues?
  20.  What is random variation and systematic variation?
  21.  What is OCV and how derates will be applied for hold analysis?
  22. Multi VT, advantages/ disadvantages of different VTs.?
  23.  Timing optimization techniques?
  24.  What is wire spreading? What will you loose using wire spreading?
  25.  What are the DRC's you see in PnR and sign-off phases?
  26. What is Recovery and Removal Time ?
  27. why minimum spacing is required between two metal wires? If this kind of violations occurs then what happens?
 Physical design Advanced interview question answers:

  1. Have you done custom CTS ? How you approach?
  2. Floor planning,Die size estimation,Macro placement.
  3. If you have some output pin and clock sinks what all you take care? 
  4. What is grid based routing and non grid based routing?
  5. What is antenna violation? Flow to fix it? Why antenna diode in reverse bias?
  6. data pulse violation, difference in glitch and data pulse,min pulse width.
  7. What is max cap and max fan out? what is it is relaxed?
  8. Which type of timing sign-off you are doing? (static / dynamic) 
  9. Is it possible to get good results due to SI?
  10. What is double switching?
  11. How to debug Shorts due to Ground connection.
  12. What is min pulse width violation.
  13. If design is in final tapout stage how will you resolve violation if they are due SI effects.
  14. If there is cloning of flop what can be issue in LEC and how to resolve it.
  15. Any special timing fix where any special solution was done.
  16. What is ESD violation. What is used for ESD violation.
  17. What is Latchup DRC and how is it resolved.
  18. What is ERC and which violation is considered in ERC.
  19. What are DFM issues.
  20. What is timing window and how is it prepared.
  21. How static and dynamic IR drop are resolved.
  22. Effect of SI on setup and hold and how.

Comments

Post a Comment

Popular posts from this blog

Special cells and their Importance

Types of cells: Well taps (Tap Cells):  This is non-logic cells. Tap cells are needed to reduce substrate and well resistance to prevent latch up. These cells generally used when the all the standard or most of the cells does not have well or substrate. - It is inserted at specific interval in the design and distance is defined as per foundry rule for specific technology.  -We can insert at every row, every other row or stagger patterns also. - Most preferable way to insert the well tap is to stagger way because of reduce the total number of cells insertion in the design and reduce the total area utilization by those tap cells.  End cap Cells:   -This are the preplaced physical only cells. -Insert to meet certain design rules -Insert at the end of the site row, top and bottom side of the block boundary and every macro boundary.  - This will also helps to reduce the drc's nearer to macros as the standard cells do not placed near to the macros.  -This cells only
Post a Comment
Read more

PD Interview Questions with Answers

PD Interview Questions with Answers: 1) How can you reduce dynamic power? – Reduce switching activity by designing good RTL - Clock gating -Architectural improvements -Reduce supply voltage -Use multiple voltage domains-Multi vdd 2) What are the vectors of dynamic power? Voltage and Current 3) How will you do power planning? 4) If you have both IR drop and congestion how will you fix it? -Spread macros -Spread standard cells -Increase strap width -Increase number of straps -Use proper blockage 5) Is increasing power line width and providing more number of straps are the only solution to IR drop? -Spread macros -Spread standard cells -Use proper blockage 6) In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why? (buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you must inser
Post a Comment
Read more

Different cells for multi Power domain designs

Special cells required for Multi-Voltage Design: (1) Level Shifter (2) Isolation Cell (3) Enable Level Shifter (4) Retention Flops (1) Level Shifter:  Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and Latch type level shifters are available. In general H2L LS’s are very simple, L2H LS’s are little complex and are in general larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths. With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale. (2) Isolation Cell:  These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an ‘always on’ region only and
Post a Comment
Read more