ASIC Flow Diagram

Special cells and their Importance

Types of cells: Well taps (Tap Cells): This is non-logic cells. Tap cells are needed to reduce substrate and well resistance to prevent latch up. These cells generally used when the all the standard or most of the cells does not have well or substrate. - It is inserted at specific interval in the design and distance is defined as per foundry rule for specific technology. -We can insert at every row, every other row or stagger patterns also. - Most preferable way to insert the well tap is to stagger way because of reduce the total number of cells insertion in the design and reduce the total area utilization by those tap cells. End cap Cells: -This are the preplaced physical only cells. -Insert to meet certain design rules -Insert at the end of the site row, top and bottom side of the block boundary and every macro boundary. - This will also helps to reduce the drc's nearer to macros as the standard cells do not placed near to the macros. -This cells only

Floorplan Stage Overview

Floorplan: Floor planing is the starting step in ASIC physical design. For example, before building the house, planning for the exact location of each end every room is similar to the ASIC’s floor planning process. Building’s blue-print planning will be a better example for ASIC floor planning. Detailed process of floor planning is explained below with necessary diagrams. Floor plan determines the size of the design cell (or die), creates the boundary and core area, and creates wire tracks for placement of standard cells. It is also a process of positioning blocks or macros on the die. First step is to define the total size of the die. Two types of design are possible. Block level designs will be rectilinear and chip level designs will be rectangular in shape. Rectilinear – To define this size more coordinates are required Rectangular – To define this only height and width of the die is required The following parameters are decided in the floor planning stage. Die size,

PD Interview Questions with Answers

PD Interview Questions with Answers: 1) How can you reduce dynamic power? – Reduce switching activity by designing good RTL - Clock gating -Architectural improvements -Reduce supply voltage -Use multiple voltage domains-Multi vdd 2) What are the vectors of dynamic power? Voltage and Current 3) How will you do power planning? 4) If you have both IR drop and congestion how will you fix it? -Spread macros -Spread standard cells -Increase strap width -Increase number of straps -Use proper blockage 5) Is increasing power line width and providing more number of straps are the only solution to IR drop? -Spread macros -Spread standard cells -Use proper blockage 6) In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why? (buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you must inser

Asic- Physical Design

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