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Standard cells placement

Placement stage during PnR:

As a basic function of placement stage is the placement of standard cells and their legalization based on certain factors. once floorplan/powerplan stage is ready then block owners need to check certain sanity checks like macro placement is proper or not, it is violating the macro spacing guidelines or not, special cells placed proper or not, port placement proper or not, power plan with all the layers incorporate in the design or not and so on. There are many other checks required to check before move to the placement stage. 

Placement stage followed by the floorplan stage.We have to set many variables related to timing/congestion analysis effort at internal stage of placement step and so on, which are depends on block complexity and user requirement. For example, if the design is critical in terms of timing, then users can set the timing optimization efforts to high from medium, so at the time of placement optimization, tool can more focus to timing and do more number of iterations to reduce the timing as much as possible. On the other hand, if we can set the timing optimization effort to high then it might be possible that congestion would be increased in the design and vice versa. If the design is more dense then you might see more degradation in congestion or if the design id not more utilized then the impact of less or might be negligible in congestion number. 

As the icc2 and innovus both tools available from the synopsys and cadence respectively. Here I am mention about synopsys tool and their internal behavior. 
There are five internal steps done during the placement step running. 

By default place_opt command doing below steps:
1) In the first step, tool prforms wire length drive coarse placement and scan chain reording. At this stage not doing any legalization. Do
2) At this stage performs high fanout synthesis and drc fixing(drc means transition at this stage)
3) Performs quick timing optimization
4) Perform incremental and final timing driven placement to improve the timing and reputability. 
5) performs final full scale optimization and legalize the design. 







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