Asic- Physical Design

Low Power Techniques: (1) Clock Gating: One-third to one-half of an IC design’s dynamic power is in the chip’s clock-distribution system.  Today, the two popular methods of clock gating are local and global . If you feed old data to the output of a flip-flop back into its input through a multiplexer, you typically need not clock again. Therefore, you can replace each feedback multiplexer with a clock-gating cell that clocks the signal off. You would then use the enable signal that controls the multiplexer to control the clock cell to clock the signal off. There are two types of clock gating: a) Latch free clock gating: b) Latch based clock gating (2) Multi-threshold technique:  TSMC  (Taiwan Semiconductor Manufacturing Co) offers a standard, or nominal, library; a high-speed library; and a low-power library, each having several types of cells. For instance, each of TSMC’s libraries includes low-threshold-voltage, high-threshold-voltage, and th

Temperature Inversion Effect: Let us first understand the basic concept of what causes the delay of the transistor from the below equation: Relation between current and delay of a mosfet   As you can find from the above that the more the current the less the delay of the PFET or NFET. Also you can refer to my previous blog on understanding the cell delay and transition. Now you understand that cell delay depends on the current. Let us see what current depends on Relation between mobility and current A phenomenon called lattice scattering happens at higher temperatures. Lattice vibrations cause the mobility to decrease with increasing temperature. Hence the resistance of a mosfet increases with increase in temperature causing current to reduce.  From the above figure we find that the current I is directly proportional to the mobility of the semiconductor. Hence as the mobility decreases, the current decreases. Hence cell delay increases. So , temperature increases ==&g

Special cells required for Multi-Voltage Design: (1) Level Shifter (2) Isolation Cell (3) Enable Level Shifter (4) Retention Flops (1) Level Shifter:  Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and Latch type level shifters are available. In general H2L LS’s are very simple, L2H LS’s are little complex and are in general larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths. With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale. (2) Isolation Cell:  These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an ‘always on’ region only and

Types of cells: Well taps (Tap Cells):  This is non-logic cells. Tap cells are needed to reduce substrate and well resistance to prevent latch up. These cells generally used when the all the standard or most of the cells does not have well or substrate. - It is inserted at specific interval in the design and distance is defined as per foundry rule for specific technology.  -We can insert at every row, every other row or stagger patterns also. - Most preferable way to insert the well tap is to stagger way because of reduce the total number of cells insertion in the design and reduce the total area utilization by those tap cells.  End cap Cells:   -This are the preplaced physical only cells. -Insert to meet certain design rules -Insert at the end of the site row, top and bottom side of the block boundary and every macro boundary.  - This will also helps to reduce the drc's nearer to macros as the standard cells do not placed near to the macros.  -This cells only