Asic- Physical Design

Floorplan: Floor planing is the starting step in ASIC physical design. For example, before building the house, planning for the exact location of each end every room is similar to the ASIC’s floor planning process. Building’s blue-print planning will be a better example for ASIC floor planning.  Detailed process of floor planning is explained below with necessary diagrams. Floor plan determines the size of the design cell (or die), creates the boundary and core area, and creates wire tracks for placement of standard cells. It is also a process of positioning blocks or macros on the die. First step is to define the total size of the die. Two types of design are possible. Block level designs will be rectilinear and chip level designs will be rectangular in shape. Rectilinear – To define this size more coordinates are required Rectangular – To define this only height and width of the die is required The following parameters are decided in the floor planning stage. Die size,

Static Timing Analysis: Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations without having to simulate . No vector generation is required ,no functionality check is done Why is timing analysis important when designing a chip? Timing is important because just designing the chip is not enough; we need to know how fast the chip is going to run, how fast the chip is going to interact with the other chips, how fast the input reaches the output etc…Timing Analysis is a method of verifying the timing performance of a design bychecking for all possible timing violations in all possible paths. Why do we normally do Static Timing Analysis and not Dynamic Timing Analysis? What is the difference between them? Timing Analysis can be done in both ways; static as well as dynamic. Dynamic Timing analysis requires a comprehensive set of input vectors to check the timing characteristics of the paths