Asic- Physical Design

PD Interview Questions with Answers: 1) How can you reduce dynamic power? – Reduce switching activity by designing good RTL - Clock gating -Architectural improvements -Reduce supply voltage -Use multiple voltage domains-Multi vdd 2) What are the vectors of dynamic power? Voltage and Current 3) How will you do power planning? 4) If you have both IR drop and congestion how will you fix it? -Spread macros -Spread standard cells -Increase strap width -Increase number of straps -Use proper blockage 5) Is increasing power line width and providing more number of straps are the only solution to IR drop? -Spread macros -Spread standard cells -Use proper blockage 6) In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why? (buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you must inser

PD interview questions ASIC physical design basic interview question answers:  ASIC design flow.  Inputs/outputs of the ASIC design flow.  What is synthesis?  What is clock jitter ?  What are the timing optimization techniques used in Synthesis?  Macro placement guidelines.  How to decide floorplan size and shape, pin placement?  What are the important checks after placement?  What is congestion ? how to reduce the congestion?  What is the difference between HFN and CTS?  What is skew and latency?  How to achieve skew and latency targets? Which is more preffered in CTS? buffers or inverters?  How to optimize the max_tran, max_cap violations. Clock balancing with generated clocks. Handle asynchronous clocks during CTS. SI issues, Crosstalk delay, crosstalk noise, What is NDR (Non-Default rule) ? How DRC will be affected due to NDR? Can you relax NDR to resolve DRC's?  Which are the DFM issues?  What is random variation and systematic variation?  What

ASIC Flow:-