Placement stage during PnR: As a basic function of placement stage is the placement of standard cells and their legalization based on certain factors. once floorplan/powerplan stage is ready then block owners need to check certain sanity checks like macro placement is proper or not, it is violating the macro spacing guidelines or not, special cells placed proper or not, port placement proper or not, power plan with all the layers incorporate in the design or not and so on. There are many other checks required to check before move to the placement stage. Placement stage followed by the floorplan stage.We have to set many variables related to timing/congestion analysis effort at internal stage of placement step and so on, which are depends on block complexity and user requirement. For example, if the design is critical in terms of timing, then users can set the timing optimization efforts to high from medium, so at the time of placement optimization, tool can more focus to timing and do
As we are moving towards the lower geometry from 45nm-28nm-16nm-7nm and so on, difficulties increasing in all the PPA aspects. This blogs will give you some idea about the PnR challenges and sign off challenges in lower geometry and ways to overcome those challenges.