Setup and Hold Analysis Example: The following figure shows setup check with late (shown in solid line) launch clock and early capture clock (shown in dotted line). Figure 1 Setup Check The following figure shows hold check with early launch clock (shown in dotted line), and late capture clock (shown in solid line). Example 1 Setup Check in BC-WC Timing Analysis Mode In the following figure the software performs setup check on the path from FF1 to FF2. The software uses the Max library to scale all delays at WC conditions. The following values are assumed in this example: Clock source latency = none wire delay = 0 clock period = 4 Clock Mode = Propagated clock mode The software computes the slack as follows: Launch clock_late_path = 0.7 + 0.6 = 1.3 Data_late_path = 3.5 Capture clock_early_path = 0.7 + 0.5 = 1.2 Setup = 0.2 Data Arrival Time = 1.3 + 3.5 = 4.8 Data Required Time = 4 + 1.2 – 0.2 = 5 Slack = 5 - 4.8 = 0.2 ...
As we are moving towards the lower geometry from 45nm-28nm-16nm-7nm and so on, difficulties increasing in all the PPA aspects. This blogs will give you some idea about the PnR challenges and sign off challenges in lower geometry and ways to overcome those challenges.