Asic- Physical Design

Setup and Hold Analysis Example: The following figure shows setup check with late (shown in solid line) launch clock and early capture clock (shown in dotted line). Figure 1 Setup Check The following figure shows hold check with early launch clock (shown in dotted line), and late capture clock (shown in solid line). Example 1 Setup Check in BC-WC Timing Analysis Mode In the following figure the software performs setup check on the path from FF1 to FF2. The software uses the Max library to scale all delays at WC conditions. The following values are assumed in this example: Clock source latency = none wire delay = 0 clock period = 4 Clock Mode = Propagated clock mode The software computes the slack as follows: Launch clock_late_path = 0.7 + 0.6 = 1.3 Data_late_path = 3.5 Capture clock_early_path = 0.7 + 0.5 = 1.2 Setup = 0.2 Data Arrival Time = 1.3 + 3.5 = 4.8 Data Required Time = 4 + 1.2 – 0.2 = 5 Slack = 5 - 4.8 = 0.2

Congestion: Congestion needs to be analyzed after placement results depends on how congested your design is. Congestion means number of required routing resources are more compared to available routing resources in the design. In simple words, number of required routing tracks is more compared to available routing tracks in the design. Routing congestion may be localized. Some of the things that you can do to make sure routing is hassle free are: Placement blockages:  The utilization constraint is not a hard rule, and if you want to specifically avoid placement in certain areas, use placement blockages. Soft blockages (buffer only) Hard blockages (No std cells and buffers are allowed to Place) Partial blockages (same as density screens) Halo (same as soft blockage but blockage can also be moved w.r.t Macro.) Macro-padding:  Macro padding or placement halos around the macros are placement blockages around the edge of the macros. This makes sure that no standard cell